The present invention relates in general to a process for etching conductive layers used in semiconductor integrated circuits (IC). In particular, the invention relates to methods for etching metal silicides, polycrystalline silicon (polysilicon) and composite silicide-polysilicon (polycide) structures and to reactive plasma gas chemistry for use in such methods.
Over the past several years, the silicon integrated circuit technologies used in manufacturing conductor-insulator-semiconductor field effect transistor (CISFET) devices and bipolar transistor devices have developed to the point that they provide very small geometry, highly dense integrated circuits. The continued improvement in silicon integrated circuit integration has been made possible by advances in the manufacturing equipment, as well as in the materials and methods used in processing semiconductor wafers and IC chips. At the same time, however, the increasingly stringent requirements imposed by the improvements in the silicon integrated circuit integration and density have strained much of the classic microelectronics processing technology. For example, with the trend toward greater device densities and smaller minimum feature sizes and smaller separations in integrated circuits, the sheet resistance of multi-level interconnects and gate electrodes and other conductors becomes a primary factor affecting frequency characteristics and power consumption, and in limiting device speed. Thus, to successfully implement greater density without adversely affecting such characteristics, it is necessary to reduce the sheet resistance of the gate and conductor materials.
Another requirement which must be met to achieve the increasingly small minimum feature sizes and minimum separations is that the lithographic pattern-transfer process must be very precise. In addition to factors such as the lithographic process itself and the wafer topography, satisfaction of this requirement necessitates in general the use of an anisotropic plasma or dry etching technology that is capable of precisely replicating the mask dimensions and size in the etched layer without degradation of the mask and loss of line width.
The two basic types of plasma etching systems--plasma etching itself in which the chemical etching component is dominant and reactive ion etching in which physical ion bombardment is dominant--are described in commonly assigned U.S. Pat. No. 4,376,672, entitled, "Material and Methods for Plasma Etching of Oxides and Nitrides of Silicon", filed Oct. 26, 1981 and issued Mar. 15, 1983. That description is hereby incorporated by reference. Of the different types of plasma etching systems, it is believed that reactive ion etching systems are the preferred systems for achieving high resolution replication of photoresist patterns, for example, in electrically conductive materials.
FIG. 1 schematically illustrates an etching system 10 that is one presently preferred system for reactive ion etching. This system 10 is available commercially from Applied Materials, Inc. of Santa Clara, Calif. as the 8100 Series System. This system 10 utilizes a cylindrical reaction chamber 11 and a hexagonal cathode 12 which is connected to an RF power supply 13. An exhaust port 14 communicates between the interior of the reaction chamber and a vacuum pump. The walls of the reaction chamber 11 and the base plate 16 form the grounded anode of this system. A supply of reactive gas from gas supply 17 is communicated to the interior of the chamber 10 through an entrance port 18 and by a conduit arrangement 19 to a gas distribution ring 20 at the top of the chamber. The reactor 10 is asymmetric. That is, the anode-to-cathode ratio is slightly greater than two-to-one, resulting in high energy bombardment of the hexagonal cathode surface 12 relative to the anode surface 11. Such a design provides lower power density and better etch uniformity, decreases contamination of and from the chamber walls and promotes a higher anisotropy. Additionally, the cathode structure configuration allows all wafers to be vertically oriented during the process to minimize wafer exposure to particulates.
Despite the availability of plasma etching systems such as the AME 8100 System 10, the microelectronics polycrystalline silicon processing technology, like the rest of the classic microelectronics technology, has been strained by the increasing levels of silicon integrated circuit integration. Polysilicon has been and is widely used in both bipolar and CISFET IC technology, for example in conductors, such as gate electrodes; in single level and multi-layer interconnects; in resistors; in buried contacts; and in the formation of emitter structures such as shallow self-aligned emitters and self-aligned emitter-contact structures. However, meeting the sheet resistance requirements in very small devices and conductors requires very high polysilicon doping levels which are obtained at the cost of isotropic etch behavior and precise pattern transfer.
Over the last several years, the microelectronics industry has been developing polycide technology as a substitute for polysilicon technology in a number of applications, in part because polycides have much lower sheet sensitivities than doped polysilicon. Polycide is a layer of metal silicide over a layer of polysilicon. Of primary interest here are the refractory metal silicides (typically disilicides): titanium silicide, TiSi.sub.x ; tantalum silicide, TaSi.sub.x ; molybdenum silicide, MoSi.sub.x ; and tungsten silicide, WSi.sub.x.